Open PCB & IC Engineer Is a Free Tool for All 3 Parts of Electronics

Electronics used to be designed in separate pieces. One team designed the chip, another the package it sits in, and a third the circuit board. Each used its own tools, and each handed its work to the next as a set of files. That is changing. Today’s fastest processors are built from several small chips, called chiplets, stacked side by side or on top of each other in one package. A decision on the chip now changes the package and the board, and the other way round, so the three have to be designed together.

The tools that can do that, such as Cadence Integrity 3D-IC, Synopsys 3DIC Compiler and Siemens Xpedition, cost six figures a year. No free tool covers it. Open PCB & IC Engineer is our answer: free, open-source software that treats the chips, the package and the board as one 3D stack.

Open PCB & IC Engineer showing KiCad's video demo board in 3D: a four-layer PCI card with large chips, connectors and memory sockets, parts drawn from their 3D models, the layer stack listed on the left — KiCad‘s four-layer “video” demo board in Open PCB & IC Engineer: copper, pads, silkscreen and the parts’ 3D models.

What it does today

The project is young. It can already open, show and save a complete design:

Circuit boards from KiCad (version 6 and later): the board outline and cut-outs, every copper layer, pads, vias, the silkscreen and the board’s layer stack, with each part drawn from its own 3D model (STEP or VRML, as in KiCad).
Chiplet designs in 3Dblox, the open format for describing how chiplets are stacked and bonded, which the open-source chip tool OpenROAD also reads. Bump maps show each solder bump between the chips.
Chip layouts in GDSII, the format chip factories take. Each metal layer is drawn at its real height above the silicon, so you can see a chip’s wiring in 3D.
Chip, package and board together: place a chiplet design inside a part on a KiCad board, and the program adds a package under it with solder balls made from that part’s pads. Then you can follow a signal from a pad on the board up into the chips.
Nets: click any copper, pad or bump and its whole net lights up through every layer, with the parts it touches listed.
Power inside the chip: the program works out the chip’s supply and ground wiring from its layout, solves how much the voltage drops and how much current each wire carries, and shows the electrons moving. It also models the whole path the power takes from the board’s regulator to the chip, capacitors included.
Signals switching: pick any signal wire and the program finds the transistors driving it and everything it has to charge, then plays it switching, with its delay; the transistors driving it can be simulated with ngspice, and its neighbours are found and lit, with the noise they cause.
Exploded view and X-ray: a slider pulls the stack apart level by level, and X-ray makes the parts see-through, so nothing stays hidden inside.
How it is built: materials, bonding methods (solder reflow, thermo-compression, hybrid bonding and others), underfill, mold and thermal paste, described in the terms of JEDEC’s JEP30 part models and drawn in place.
Saving in open formats: designs are saved as standard 3Dblox, plus one small extra file for what 3Dblox cannot hold. We check the saved files with OpenROAD’s own 3Dblox readers, so other tools can open them.

A close view of the same board darkened, with one PCI bus line glowing cyan from a gold edge-connector finger, through a via, to the large chip — Pick a net and it lights up through the whole stack: here one PCI bus line, from the edge connector to the chip.

An IHP SG13G2 SRAM layout opened from GDSII, its metal layers pulled apart above the grey silicon — A real chip layout (IHP’s open SG13G2 SRAM, 1.8 million shapes) pulled apart layer by layer above the silicon.

Big layouts open quickly. The SRAM above, with 1.8 million shapes, appears in under a second; what you look at sharpens over the next few seconds, the way an online map fills in as you zoom, and is kept on disk so it opens even faster next time. (It used to take 14 seconds.) The mouse wheel zooms toward whatever is under the cursor, and every view change glides smoothly instead of jumping.

Walk through a chip

Press W and you are inside the chip. You stand in one of its metal layers, between the wires, which rise around you like the walls of a building. The gaps between them become hallways. The program guides you as you walk: it keeps you in the middle of the hallway, turns with it, stops you short of a wall, and takes you into the next side hallway when you press an arrow key.

Walk mode inside the SRAM's fourth metal layer: a wide hallway between two gold metal walls stretching to the horizon, with grey via pillars standing on the cyan third-layer wires below — Walk mode: standing inside the chip’s fourth metal layer, between two of its wires. The grey pillars are vias, the vertical links down to the cyan wires of the layer below.

Page Up / Page Down work like an elevator, one floor up or down. The floors are the chip’s via layers: rows of pillars that stand on one layer of wires and hold up the next, with a label showing which floor you are on.
Space bursts through the wall straight ahead into the next hallway.
A click with the mouse wheel on any shape, from outside or from inside, puts you on top of it: you can climb onto a wall and walk along it.
A label shows which layer you are in, and Esc glides you back out to where you were.

Walk mode on a floor of the chip: grey via pillars stand in rows on magenta second-layer wires, under a ceiling of cyan third-layer wires, with a label reading Floor 3 of 4, Via2 — Page Up and Page Down are an elevator. Each floor is a layer of vias: grey pillars standing on one layer of wires (magenta) and holding up the next (cyan).

Walk mode in the SRAM's first metal layer: a narrow corridor between blue metal walls, the transistors' red gates and green active areas visible on the floor far below — The first metal layer, just above the transistors: a narrow hallway, with the transistors’ red gates and green active areas on the floor.

We find it the clearest way yet to understand how a chip is wired, and to show someone who has never seen the inside of one.

Watching electrons move

A chip’s supply does not arrive everywhere at full strength. It spreads from the pins through a mesh of metal, and every wire and via in that mesh has a little resistance. Where many transistors draw current at once, the voltage they get sags. Chip designers call this IR drop and usually see it as a table of numbers or a flat colour map. We wanted to see it.

Open PCB & IC Engineer reads the layout, works out which shapes are joined into each net, and turns the supply (VDD) and ground (VSS) metal into a network of resistors, using each layer’s sheet resistance and each via’s resistance from the chip factory’s own data. On the SRAM above that is more than a million pieces per rail, solved in seconds. Then the electrons start to move.

Animation: thousands of small white spheres drifting along the rows of blue metal rails of an SRAM's power grid, seen at a slant, some faster than others, with greener metal in the far corner where the voltage has dropped — Virtual electrons drifting through the power grid of an SRAM block in IHP’s open 130 nm process. Brighter spheres move faster.

These are virtual electrons. A real wire carries more electrons than anyone could count, and each one wanders about at random, only slowly drifting one way. Drawing them all is impossible, and it would show nothing anyway. So each sphere on the screen stands for the crowd around it, and it moves the way the crowd does on average:

Against the current. Electrons carry a negative charge, so they move opposite to the “conventional” current of textbooks, which flows from + to −. If you prefer the textbook view, one click switches to dots streaming the conventional way.
As fast as the current is crowded. A sphere’s speed follows the current density: the current divided by the wire’s width and thickness. A thin wire low in the chip carrying the same current as a thick one higher up shows faster electrons, as it really does.
Up and down through vias, as often as each via carries the current there, so you can watch electrons arrive through the supply and leave through the ground.
Not to scale. The spheres stay a few pixels across at any zoom; real electrons are far smaller than any wire. Their speed is relative, too. The colour key gives the real drift for copper: in the busiest metal of this chip, about 7 millimetres a second, slower than an ant walks. What crosses the chip at nearly the speed of light is the push passed from one electron to the next, not the electrons themselves.

Under the electrons, the metal is coloured by how far the voltage has dropped there, or by how close each wire is to the most current it can safely carry. Rest the mouse anywhere for the numbers: the drop in millivolts, the current per micron of wire, and the share of that layer’s limit.

Through a clock cycle

A chip does not draw a steady current. Most of it comes in a burst just after each tick of the clock. The program solves the grid’s answer once for each block of the chip, then mixes those answers moment by moment, so a whole clock cycle can be played back, slowed down, paused or scrubbed, with the electrons surging and settling as it goes.

Animation: the same power grid of blue metal rails through one clock cycle; after each clock edge the white spheres surge forward and the metal shifts toward green as the supply sags, then they settle again — The same grid through one clock cycle, played slowly. After each clock edge the current surges, the electrons speed up, and the metal turns from blue toward green as the supply sags.

The currents in this animation come from a simple clock model, to illustrate the idea, and the screen says so. Currents from a real circuit simulation, saved from ngspice or any simulator as a table, drive it instead and make it real.

Pretty pictures are only worth something if the numbers under them are right, so we check them. The solver matches all six of IBM’s published power-grid benchmarks, the largest with 1.67 million points, to the rounding of IBM’s own answers. Its time stepping matches IBM’s changing-current benchmark (ibmpg1t) within 0.073 mV on a swing of 216 mV, and runs in about a second.

What a failed capacitor does inside the chip

The chip’s power starts at a regulator on the board and passes through the board’s copper, the decoupling capacitors and the package before it reaches the pins. Each of those capacitors can now be set as good, open, shorted, short of capacitance or high in resistance (ESR), and the effect shows inside the chip at once. The capacitors can be read straight from the KiCad board, and the window plots the impedance the chip sees from 1 kHz to 10 GHz.

The Power Path window: a chain from the regulator through the board, decoupling capacitors and package to the die, one 0.01 microfarad capacitor set to open, and a plot of impedance against frequency — The power path, with one 0.01 µF capacitor set to open. The plot shows the impedance the chip sees at its pins from 1 kHz to 10 GHz, against the target and the clock.

In one example, opening a single 0.01 µF capacitor raised the worst squeeze the transistors feel (the supply’s drop plus the ground’s bounce) from 114 mV to 144 mV. The example uses the simple clock model, so the numbers show the method, not a real product. One lesson held in every try, though: whether a missing capacitor hurts depends on how its resonance lines up with the clock. In one case, taking a capacitor away made things better. That kind of surprise is easier to believe when you can watch it happen.

A signal switching

Power is not the only thing that moves. Every signal wire in a chip is a tiny capacitor: each time it switches on, the transistor driving it has to pull electrons out of the wire and out of the transistor gates the wire feeds, and each time it switches off, it pushes them back. The program now finds a signal’s drivers and everything they have to charge. The wire’s share comes from IHP’s published layer data; the gates’ share comes from the thickness of the gate oxide in IHP’s transistor models.

Animation: close-up of one word line in an SRAM, a long blue wire with short posts hanging below it down to the transistor gates; at each switch white spheres swarm along it and the posts glow yellow and orange, then fade back to blue — One word line of the SRAM switching at 500 MHz, played slowly. Each time it switches on, its driver pulls electrons out of the line and out of the transistor gates it feeds (the posts below it); each time it switches off, it pushes them back. Yellow and orange mark the places still lagging behind the driver.

This is a word line, the wire that wakes up one row of memory cells. Counting only its metal wiring, as if it ran alone, it holds 56.5 femtofarads: 16.9 in that wiring and 39.6 in the gates it reaches (its poly wiring and its neighbours add more: see below). The signal takes at most 2.5 picoseconds to travel along the wire, small next to the time its driver takes to switch it (more on that below). As with the power grid, we checked the method by hand. On a simple test wire with one gate at its far end, the program’s capacitances match the hand calculation, and its delay comes to 0.480 picoseconds against 0.477 by hand.

The transistors doing the work

A wire is only as fast as the transistors driving it, so the program now reads those from the layout too: how wide and how long each one is, and whether it is an NMOS or a PMOS transistor. PMOS transistors pull a signal up to the supply and NMOS ones pull it down to ground, each through a resistance set by its size. The resistance per micron of width comes from the transistor currents in IHP’s process specification.

Real logic gates often stack their transistors. In a NAND gate, two NMOS transistors sit in series, so their resistances add, while its PMOS transistors sit side by side and only one of them may be on. The program follows every path of up to four transistors from the wire to the supply or to ground, works out which gates must be on for each path to conduct, and takes the slowest case, as timing engineers do.

The word line above has a strong pull-up, so it switches on in about 77 picoseconds and off in about 155 (about 116 and 235 once all of its wiring and its neighbours are counted). For the memory’s read clock, its designers made the PMOS transistors 2.3 times as wide as the NMOS ones, close to the 2.2 ratio of their currents in IHP’s specification, and the program shows the result: rising and falling edges almost exactly equal.

To check all this, we simulated each driver with ngspice, the open-source circuit simulator, using IHP’s own transistor models. The program’s delays land between 3 percent fast and 31 percent slow, usually about 10 percent slow. Its edges come out somewhat slow, because a real transistor charges a wire at a nearly steady current rather than along the dying-away curve of the simple model. So the program can now hand the job to ngspice itself: with one click, the drivers are simulated at their real sizes with the real models, and the electrons follow the simulated current.

Some wires have many drivers that take turns. A bitline in a memory runs past every cell in its column, and only the cell being read drives it. The program now lets you choose which one drives:

Animation: a long bitline of an SRAM running diagonally across rows of wiring; at each read it lights up white as electrons stream out of one memory cell at the lower right and spread along it, then it fades back — One memory cell reading. It pulls the bitline down, so electrons stream out of the cell (lower right) and spread along the bitline. The cell’s current comes from ngspice with IHP’s transistor models, played slowly. The recharge that follows is simplified: it is drawn through the same cell, while a real memory recharges its bitlines from a separate circuit.

A single memory cell supplies only about a tenth of a milliamp, so pulling the whole bitline down would take more than a nanosecond. Real memories do not wait for that: a sense amplifier notices a small swing long before the bitline gets there. Seeing it this way makes it clear why they need one.

Neighbours that talk to each other

Wires in a chip are packed so tightly that each one forms a small capacitor with its neighbours, not just with the silicon below. When a neighbour switches, it pushes a little charge across the gap, and the wire next to it gets an unwanted bump in voltage. Engineers call this crosstalk. The program now finds every wire beside, above and below a signal, at any angle and on every layer, including the polysilicon, works out how strongly each one is coupled to it, and lights up the worst three.

Animation: the same word line switching, its electrons streaming along it, with a white wire running close beside it on one side and a pink wire with posts on the other — The word line again, now with its two closest signal neighbours lit: another word line in white and a second one in pink. Each time either of them switches, it pushes a little charge onto this one through the narrow gap between them.

Counting everything raises the word line’s load from 56.5 to 87 femtofarads. Of those, 34 are coupling to its neighbours: 39 percent of everything its driver has to charge, most of it to the supply and ground lines laid beside it. (The neighbours also shield it from the silicon below, so that share shrinks.) Another 10 come from its polysilicon wiring outside the transistors. Together they move its switching time from about 77 to about 116 picoseconds. If every signal next to it switched at the same moment, their bumps would add up to 88 millivolts, about 7 percent of the 1.2-volt supply and well inside what a logic gate can ignore.

Elsewhere it matters more. The memory’s read clock runs right beside its write clock for 124 microns, and the write clock alone can bump it by 63 millivolts. The bitlines are the most sensitive of all, because one tiny memory cell has to hold each of them steady. That is why the memory’s designers ran supply lines between them as shields, and the program shows that most of their coupling goes to those shields.

Where do the coupling numbers come from? IHP publishes rules for Magic, an open-source layout tool, but at the closest spacing a chip allows they give about twice what the physics says. So we wrote a small field solver that works out the electric field around a wire and its neighbours. We checked it against a single wire and against a published formula, then fitted every metal layer from it. A check against a full 3D solver is still to come. These numbers will also matter later: when the program routes wires itself, it will use them to keep fast signals from running side by side.

Why build all this? Because we want students, and anyone curious, to see what engineers usually only calculate. When a young engineer watches electrons crawl through a wide rail and race through a narrow one, the formulas start to mean something.

Your designs stay yours

A chip’s layout is among the most valuable things its maker owns, and many makers keep it secret. Open PCB & IC Engineer respects that. It works on your own computer: it reads your files there and sends nothing anywhere. The program contains no network code at all.

Companies still need to work together: a customer building a package or a board around your chip needs its size, its connections and how it is built, not its wiring. For that, File → Export Shareable Model offers two choices:

Protected model, for customers. It keeps the outline, the bumps and pins with their connections, the layer stack, the materials and how the chip is bonded. Each chip layout is replaced by a density map that shows how much metal lies in each 2-micron square of each layer, but not the wires themselves. The layout files, their names and every link to your own files are left out. Your customer can still place the chip, check the connections and even walk through it, as a building of blocks.
Complete design, for partners who may see everything: the full layouts are copied in with the design, ready to send.

The same SRAM opened from a protected shareable model: the chip's layers shown as coloured blocks of density instead of individual wires — The same SRAM from a protected shareable model: the layers show where the metal is, square by square, but not the wiring itself.

The protected model is saved in the same open formats as any design, so it is just as easy to pass on. We hope it makes sharing an easy yes for chip makers: their customers can design with their chips sooner, and nothing they would regret leaves the building.

Open formats, so designs never get locked in

A design you make in Open PCB & IC Engineer belongs to you, not to us. It reads and writes the formats the rest of the industry uses, and it keeps its own additions in a separate file, so a strict 3Dblox reader never meets anything it does not know. KiCad stays the home of your board: the program reads the board from KiCad’s own file instead of copying it.

Sometimes a standard cannot yet carry what a real design needs. JEDEC’s JEP30, for example, says what underfill is made of but not where it goes. When that happens we do not invent a private format and keep it to ourselves. We write a proposal to the committee that maintains the standard. Our first one, nine additions to JEP30 for chiplet and 3D designs, is on our Standards Proposals page.

A two-chiplet design: two blue dies on a green interposer, with its instances, definitions and connections listed — A 3Dblox chiplet design: two dies on an interposer, with the bonds between them.

Where it is going

What exists today is the first of seven steps. Next on the electrons’ side: the board’s own copper planes feeding the power model, and the rest of the capacitance work, so the logic itself comes alive. The steps after that are:

a stack editor for defining the chips, package and board and how they connect: bumps, balls and through-silicon vias;
checks across the stack: is every connection made from chip to package to board, and do the layers line up and keep their distance?
editing of layouts on any level, in 2D and 3D, and drawing schematics;
driving proven engines instead of rewriting them: OpenROAD to place and route the chips, and ngspice to simulate the circuit;
co-design: heat and signal estimates, and help deciding what belongs on which chip, in the package or on the board, including chip pinouts planned from the start so chips can be stacked with their connections running straight up, weighing the noise every moved pin adds;
output for manufacturing (GDS and OASIS for chips; Gerber, ODB++ and IPC-2581 for boards; STEP for mechanical design), with installers for Linux and Windows.

Articles

In-depth articles on how parts of Open PCB & IC Engineer work, and how they came to be. The list grows as the work does.

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Beta 0.2 Starts Now

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Free software

Open PCB & IC Engineer is free software under the GNU General Public License, version 3, from The JCArtes Foundation. It is written in C++ with Qt 6 and runs on Linux today. The source code is not public yet; we will publish it, with downloads, here on JCArtes.Org once the first version is ready to try.

Do you design chips, packages or boards, or teach people who do? We would like to hear what you need. Write to Support@JCArtes.Org.