JEP30 Proposal: 3D and Chiplet Assembly

Status: draft for discussion, published 15 October 2026.

From: Arthur Baldwin, The JCArtes Foundation, for Open PCB & IC Engineer (PCBICEng), a free (GPL v3) 3D PCB and IC co-design tool. Contact: Support@JCArtes.Org

To: JEDEC JC-11 Committee on Mechanical Standardization (JEP30 Part Model Guidelines). Thermal items are also for JC-15.

Based on: JEP30G.01 (Dec 2025), JEP30-T100C and JEP30-S100B (Sep 2025), and schema set v10-0-0 (PartModel 10, P101 10, PX101 2, K101 2.1, D10 7, E101 6.1, T101 4). Newer revisions may already cover some of these points. If so, please tell us.

Who We Are and Why We Are Writing

PCBICEng is a desktop EDA tool for designing chiplet and 3D-IC assemblies together with the board they sit on. It reads and writes 3Dblox, the assembly format that OpenROAD reads, and KiCad boards and GDSII layouts. It shows the whole stack in 3D, from die metal layers through interposer and package to board. It is free software under GPL v3, and its source code will be published.

We want JEP30 to be the tool’s part, material and process library: what each die, package and substrate is, its terminals, materials and bonding technologies. 3Dblox would stay the design: which parts are placed where and what connects to what. JEP30’s terms are already in our data model. Our materials, part functions, die-level and board-level assembly technologies, interconnect methods, terminal functions and compound kinds use JEP30’s element names and enumeration values, so a JEP30 file can map onto a design without loss.

While building this we found information that a 3D or chiplet design needs but that JEP30 cannot yet carry. For each item below we hold the data in our own extension file today. We would much rather the industry format carried it, so we offer each item as a proposal, with our working form as an example.

Summary of Proposals

#	Proposal	Section in JEP30	Priority
P1	Connectivity inside a Product: which terminal group of one component bonds to which of another, with the bond gap and the interconnect used	PX101 Stack / Assembly	High
P2	Compound placement geometry: where underfill, mold, TIM and lid attach go, and how far they reach	PX101 Compound / CompoundPlacement	High
P3	3D-IC die structures: TSVs, backside terminals and backside power, hybrid-bond pad pitch and overlay tolerance	P101 Die	High
P4	Die power maps, and product-level thermal boundary conditions	T101 (JC-15)	Medium
P5	Die-to-die link constraints and channel-model references	E101	Medium
P6	Full substrate stack-up: material, thickness and copper per layer	PX101 Substrate / Construction	Medium
P7	Process layer table for a die: layer number, z and thickness, linking to the layout	P101 Die MaterialStackup	Medium
P8	A compact external form for very large terminal arrays	P101 / PX101 terminal patterns	Low
Q1	Licence question: open-source readers and writers written from the schemas	Policy	—

P1. Connectivity Inside a Product

Gap. A Product places components in a Stack (levels, ZIndex, flip, rotate, offset). It also gives each component its assembly technology, and a Die-LevelAssemblyTechnology names the interconnect: mass reflow, TCB, hybrid bonding and so on. But nothing says which terminal group of the top component meets which terminal group of the one below. Nothing gives the bond gap, or which interconnect each individual bond uses when a component has more than one. A Product file therefore cannot be checked for alignment or for net continuity, and it cannot drive a thermal or mechanical model of the bond layer.

Proposed addition. Under the Product Assembly, add a Bond list. Each bond would give:

a top end and a bottom end, each a component placement ID plus a TerminalGroup or region ID (the bottom may be empty for a free-standing part);
the gap (nominal plus tolerance), and an AssemblyTechnologyID or inline DieInterconnect;
optionally, a net or signal-map reference for the bonded terminals.

Our working form. The top and bottom ends come from the 3Dblox Connection element, and the PCBICEng extension file adds the interconnect:

# 3Dblox (design)                     # PCBICEng extension
Connection:                           connections:
  cpu0_attach:                          cpu0_attach:
    top: cpu0.regions.front               interconnect: ThermoCompressionBonding
    bot: base.regions.front               material: SAC305
    thickness: 30.25

P2. Compound Placement Geometry

Gap. A Compound has a kind (Underfill, Overmold, Potting, HermeticSealing, LidAttach, ThermalInterfaceMaterial) and a material. A CompoundPlacement puts it at a stack level. It has no extent: nothing says how far an underfill fillet spreads or climbs, how thick the mold cap over the top die is, or which components a mold or TIM covers. Warpage, thermal and keep-out checks all need these numbers.

Proposed addition. Give a CompoundPlacement:

the bond (P1) it fills, or the component placements it covers;
a margin beyond their outline;
a height (fillet height for underfill; cap thickness for the others).

Each value would be Nominal plus a Rule, as elsewhere in JEP30. A later revision could add fillet shapes (straight or meniscus) or a STEP reference.

Our working form:

compounds:   # lengths in µm
  - {name: uf0,  kind: Underfill, connection: cpu0_attach, margin: 40, height: 30}
  - {name: mold, kind: Overmold,  material: EMC, instances: [cpu0, cpu1], margin: 100, height: 200}
  - {name: tim,  kind: ThermalInterfaceMaterial, material: TIM-Grease, instances: [cpu0, cpu1], height: 50}

Our rule for drawing them:

Underfill fills the bond gap under the top part, margin wider all round, and climbs height up the part’s sides.
Mold, potting and seals wrap the covered parts from the lowest bottom to height above the highest top.
TIM and lid attach are a layer height thick on the highest top.

P3. 3D-IC Die Structures

Gap. The Die model has a material stack-up, metallization, protective coating, terminal styles and an active zone. For stacked dies it lacks:

TSVs: diameter, pitch, depth, liner, keep-out zone, and the array or pattern they form;
backside terminals and backside power delivery: terminals on the die’s back face, and backside metal layers;
hybrid-bond pad specifics: pad size, pitch, recess or protrusion, and the die-to-die overlay and alignment tolerance the bond needs;
RDL layers on the die.

Proposed addition. Under Die:

a TSV element: geometry (Nominal and Rule), pattern, keep-out, and a MaterialID for the fill and the liner;
backside terminal groups, using the existing terminal patterns with a side attribute;
an alignment tolerance in the die-level assembly technology for hybrid bonding and TCB.

P4. Die Power Maps and Product Thermal Boundary Conditions (JC-15)

Gap. The thermal section carries package-level compact models (DELPHI, two-resistor, reduced-order). Chiplet co-design needs the power density across each die (by block or on a grid), plus boundary conditions for the whole product. Without them, hot spots in a stack cannot be modelled from the part data.

Proposed addition. Under the die thermal data, a power map:

by block (rectangles with power) or as a regular grid;
for named operating conditions;
or a reference to an external file in an agreed format.

P5. Die-to-Die Link Constraints

Gap. The electrical section names the chiplet interfaces (UCIe, BoW, AIB, HBM, OpenHBI) with their standard signal names. It can also reference SPICE and IBIS models. It does not carry the channel limits the routing must meet: maximum length, skew within a group, impedance, insertion-loss budget. It also has no reference to an S-parameter channel model.

Proposed addition. Per interface instance: a constraint set (Nominal and Rule values), and an optional Touchstone file reference with its port map.

P6. Full Substrate Stack-Up

Gap. Substrate Construction gives the base material, core and build-up layer counts, and the thickness. Signal integrity, warpage and thermal analysis need each layer: its material, its thickness, and its copper weight or plating.

Proposed addition. An ordered layer list in Construction. Each layer gives a type (conductor, dielectric, solder mask, core), a MaterialID, a thickness (Nominal and Rule) and copper coverage. The counts stay, as a summary.

P7. Die Process Layer Table

Gap. MaterialStackup and DieMetallization give thicknesses by level. To draw or analyse a die from its layout, a tool also needs each layer’s GDS layer and datatype number, its z above the silicon and its passivation thickness. With these, the stack-up links to the layout data.

Our working form, built from IHP’s open SG13G2 process data:

technology: IHP SG13G2
unit: micron
passivation: 1.9
layers:
  - {name: Metal1, gds: [8, 0],  z: 1.04, thickness: 0.42, kind: metal}
  - {name: Via1,   gds: [19, 0], z: 1.46, thickness: 0.54, kind: via}

Proposed addition. Optional LayoutLayer (layer and datatype) and z fields on stack-up entries.

P8. Compact Form for Very Large Terminal Arrays

Hybrid-bonded dies can have 10⁵ to 10⁶ terminals. Writing irregular arrays as one XML element per terminal makes files very large. We propose an optional external terminal-map reference: a flat table of name, x, y, terminal type and signal, like 3Dblox’s .bmap. It would sit next to the existing patterns, with a hash so the digital signature still covers it.

Question on Licensing (Q1)

The JEDEC terms of use treat files converted from the JEP30 schemas as derivative works. We would like to ship a JEP30 reader and writer in our GPL v3 tool, written by hand from the published schemas and guidelines. No code would be generated from the XSDs, and we would not redistribute the schema files.

Is this acceptable to JEDEC? If not, which licence terms would allow an open-source implementation? An open reference implementation would help JEP30 adoption among smaller design houses and in academia.

Other Requests

Example files. Are there public JEP30 instance files, such as vendor part models, that we could test a reader against?
Coordination with 3Dblox / IEEE P3537. 3Dblox carries placement and connectivity but no materials or bonding methods. JEP30 carries the reverse. A short mapping note between the two would help every tool that needs both. We are glad to draft one.
Participation. We would like to take part in the JEP30 task group, or comment on drafts, as an implementer.

The working forms above come from PCBICEng and run today. The JEP30 element names used here come from the published guideline and schemas, and are cited only to identify where each addition would go.

Back to Standards Proposals. Comments are welcome at Support@JCArtes.Org.